Electronic circuits, such as integrated microcircuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microcircuit devices typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit being designed, its complexity, the design team, and the microcircuit fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” will verify a design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected.
Several steps are common to most design flows. Initially, the specification for the new microcircuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). The logical of the circuit is then analyzed, to confirm that the logic incorporated into the design will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. This logical generally corresponds to the level of representation displayed in conventional circuit diagrams. Preliminary timing estimates for portions of the circuit may be made at this stage, using an assumed characteristic speed for each device. In addition, the relationships between the electronic devices are analyzed, to confirm that the circuit described by the device design will correctly perform the functions desired for the circuit. This analysis is sometimes referred to as “formal verification.”
Once the relationships between circuit devices have been established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design, a “physical” design or a “physical layout” design. The geometric elements define the shapes that will be created in various materials to actually manufacture the circuit device components (e.g., contacts, gates, etc.) making up the circuit. While the geometric elements are typically polygons, other shapes, such as circular and elliptical shapes, also may be employed. These geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Geometric elements also are added to form the connection lines that will interconnect these circuit devices. Layout tools (often referred to as “place and route” tools), such as Mentor Graphics' IC Station or Cadence's Virtuoso, are commonly used for both of these tasks.
With a layout design, each physical layer of the microcircuit will have a corresponding layer representation, and the geometric elements described in a layer representation will define the relative locations of the circuit device components that will make up a circuit device. Thus, the geometric elements in the representation of a metal layer will define the locations in a metal layer where conductive wires used will be formed to connect the circuit devices. Typically, a designer will perform a number of analyses on the layout design, which are sometimes referred to as “physical verification.” For example, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships described in the device design. The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements. Still further, it may be modified to include the use of redundant or other compensatory geometric elements intended to counteract limitations in the manufacturing process, enhance the optical resolution of the lithographic masks that will be created from the design, etc.
After the layout design has been finalized, then it is converted into a format that can be employed by a mask or reticle writing tool to create a mask or reticle for use in a photolithographic manufacturing process. Masks and reticles are typically made using tools that expose a blank reticle to an electron or laser beam. Most mask writing tools are able to only “write” certain kinds of polygons, however, such as right triangles, rectangles or other trapezoids. Moreover, the sizes of the polygons are limited physically by the maximum beam aperture size available to the tool. Accordingly, larger geometric elements in the layout design, or geometric elements that are not basic right triangles, rectangles or trapezoids (which typically is a majority of the geometric elements in a layout design) must be “fractured” into the smaller, more basic polygons that can be written by the mask or reticle writing tool. Once the layout design has been fractured, then the layout design data can be converted to a format compatible with the mask or reticle writing tool.
Because of the complexity of modern integrated circuit designs, a design plan for an integrated circuit is often broken up into design blocks (or even smaller units referred to as “cells”). Separate teams of designers can then create the design (including the physical layout design) for each block, and the completed physical layout design blocks are assembled into a physical layout design for the entire integrated circuit. As the design teams begin to assemble their physical layout design blocks into a design for the entire integrated circuit, however, the task of physical verification becomes more difficult. New errors can appear in the context of the whole design that were not present when verifying the component cells or blocks in isolation. These errors must be addressed (i.e., “debugged”) before the physical layout design for the complete integrated circuit can be approved for manufacturing. Accordingly, verifying and approving a physical layout design for an entire integrated circuit, sometimes referred to as “sign-off,” is a lengthy process falling at the end of the integrated circuit design cycle, when delays can mean the difference between meeting or missing a design project's deadline.
While the task of integrated circuit physical design assembly and verification has traditionally been the responsibility of a select number of individuals who can address errors in the combined physical layout design that occur due to the interactions between component cells or blocks, the entire design group typically must work closely together to achieve this task. With conventional design techniques, design teams collaborate using a host of traditional methods. These may include written lists, both paper and electronic, team meetings, multiple emails and of course personal visits interactions to discuss various approaches for addressing errors in the design. These conventional design techniques can be laborious and time-consuming, however, and their efficiency is highly dependent upon the personal management skills of both the design team leaders and the individual members of the design team.